1. Field of the Invention
The present invention relates generally to a method of manufacturing a package substrate with a fine circuit pattern using anodic oxidation. More particularly, the present invention relates to a method of manufacturing a package substrate with a fine circuit pattern, which is achieved by forming open areas on a metal core through a masking process, and forming oxidation layers on the open areas through anodic oxidation, and electro-copper plating portions between the oxidation layers or filling paste between the oxidation layers.
2. Description of the Related Art
Generally, printed circuit boards (PCBs) are manufactured through the following processes. That is, a thin film made of copper or the like is attached to a surface of an insulation plate made of a phenol or epoxy resin. Next, the insulation plate with the thin film is etched according to a wiring pattern of a circuit such that parts other than the circuit are eliminated, so that a required circuit is obtained. Afterwards, holes are bored for mounting components.
That is, the PCB functions to electrically interconnect the components mounted according to the wiring pattern. Further, the PCB serves to supply electricity to the components and mechanically support the components.
Recently, as miniaturization and thinness of the PCB are increasingly required in various fields including industrial equipment, office equipment, communication equipment, broadcasting equipment, and portable computers, especially, mobile communication equipment and digital household electric appliances, packaging technology, such as micro ball grid array (BGA), tape carrier package (TCP), and chip size package (CSP), has been developed. Thus, those skilled in the art take a growing interest in a method of manufacturing the package substrate on which a chip is mounted, using the above-mentioned packaging technology.
The method of manufacturing a package substrate through a conventional build-up method will be described in detail with reference to FIGS. 1a to 1k. 
In this case, the build-up method is defined as a method wherein an inner layer with a circuit pattern is formed, and outer layers are laid on the inner layer one by one.
First, as shown in FIG. 1a, an insulation layer 11 is provided, and copper foil layers 12 are placed on both surfaces of the insulation layer 11 so that the insulation layer 11 is interposed between the copper foil layers 12. Thereby, a copper clad laminate 10 is prepared.
The copper clad laminate 10 is a substrate for fabricating a PCB, and is configured such that copper 12 is thinly coated on both surfaces of the insulation layer 11. A glass/epoxy copper clad laminate is used as the copper clad laminate 10.
Next, as shown in FIG. 1b, a via hole 13 is formed on the copper clad laminate 10 through a drilling process. The via hole 13 functions to electrically connect several layers to each other. Subsequently, electroless copper plating or electrolytic copper plating is carried out to form a plating layer 14 on the copper foil layers 12 and the via hole 13, as shown in FIG. 1c. 
After the electroless copper plating or electrolytic copper plating is carried out, paste 20 is filled in the via hole 13 to protect the plating layer 14 which is formed on an inside wall of the via hole 13, as shown in FIG. 1d. 
In this case, insulating ink material is usually used as the paste 20. However, conductive paste may be used according to an intended purpose of a PCB.
After the paste 20 is filled in the via hole 13, an etching resist pattern 30 is formed so as to form an inner layer circuit pattern on the plating layer 14 of the copper clad laminate 10, as shown in FIG. 1e. 
In order to form the etching resist pattern 30, a circuit pattern printed on an artwork film must be transferred to the copper clad laminate 10. To date, several transferring methods have been used. However, a transferring method using a photoresist dry film is the most widely used. According to this method, the circuit pattern printed on the artwork film is transferred to the dry film by ultraviolet rays.
In this case, the dry film to which the circuit pattern is transferred serves as an etching resist. Thus, when the etching process is carried out, a portion of the plating layer 14 without the etching resist pattern 30 is eliminated. Thereby, a base substrate with a predetermined inner layer circuit pattern 15 is obtained, as shown in FIG. 1f. 
Thereafter, in order to form a predetermined build-up layer on the base substrate with the inner layer circuit pattern 15, a resin layer 40 is laminated to provide an interlayer electrical insulation, as shown in FIG. 1g. Subsequently, as shown in FIG. 1h, a blind via hole 50 is formed on the resin layer 40 to electrically connect the inner layer circuit pattern 15 formed on the base substrate and an outer layer circuit pattern which will be described later.
In this case, the blind via hole 50 may be formed through a mechanical drilling method. However, since the blind via hole 50 must be more precisely machined compared to a through hole, it is preferable that the blind via hole 50 be formed using a yttrium aluminum garnet (YAG) laser or CO2 laser.
After the blind via hole 50 is formed, the blind via hole 50 is plated with copper. Simultaneously, a plating layer 60 on which a predetermined outer layer circuit pattern is formed is provided, as shown in FIG. 1i. 
Thereafter, a masking process is carried out to form an outer layer circuit pattern on the plating layer 60, as shown in FIG. 1j. Finally, photo imageable solder resist mask (PSR) ink 70 is coated as shown in FIG. 1k, thus protecting the outer layer circuit pattern 61 formed on the plating layer 60, and preventing the formation of a solder bridge on the outer layer circuit pattern 61, during a soldering process. Accordingly, a final package board is completed.
As described above, the method of manufacturing the package substrate using a semi-additive method wherein the copper clad laminate 10 is used as a core layer and the build-up layers are laid on upper and lower surfaces of the copper clad laminate 10, has the following problems. That is, since the copper clad laminate 10 is used, the thickness of the package substrate is inevitably increased, and thereby it is impossible to comply with requirements for an increase in signal processing speed and package density and miniaturization of a system, and it is difficult to realize system-in-package.
Further, the conventional method of manufacturing the package substrate according to Korean Laid-Open Publication No. 2003-73919 has the following problems. That is, since electrolytic copper is laid on a seed layer through electroless plating, and then a fine circuit is formed using the dry film, it is impossible to achieve a fine circuit pattern of 50 micrometers or less. Further, as the fineness of the circuit pattern becomes higher, delamination of the dry film frequently occurs, thus causing a defective product.